Aspera Achieves 10 Gbps WAN Transfer Speeds on High-End Intel Platforms in Virtualized Environments

Aspera high-speed faspTM technology powered by Intel® Xeon® processor E5-2600 product family-based systems with Intel® Data Direct I/O Technology (Intel® DDIO) delivers superior transfer performance for high-performance computing environments.

BOSTON—BioIT World 2013, Booth 234, April 9, 2013 —Aspera, Inc., creators of next-generation software technologies that move the world’s large data at maximum speed, have announced the results of a joint research project with Intel Corporation to investigate  high-speed (10Gbps and beyond) data transfer solutions built upon Intel® Xeon® processor E5-2600 product family-based systems and Aspera’s fasp transport technology.

The results published in a joint Aspera and Intel whitepaper show superior Aspera transfer performance on Intel platforms equipped with the novel Intel® Data Direct I/O Technology  (Intel® DDIO) which allows Intel® Ethernet controllers to route I/O traffic directly to the processor cache and built-in support for Single-Root I/O Virtualization (SR-IOV) including approximately the same throughput in both virtualized and physical computing environments:

  • 300 percent throughput improvement versus a baseline system that did not contain support for Intel® DDIO and SR-IOV, showing the clear advantages of Intel’s innovative Intel® Xeon® processor E5-2600 product family.
  • Similar results across both LAN and WAN transfers confirming that Aspera fasp transfer performance is independent of network latency and robust to packet loss on the network.
  • Approximately the same throughput for both physical and virtualized computing environments.

One of the major challenges in high performance cloud computing is the capability of moving big data in and out of the backend data center, especially across increasingly virtualized environments. Today high-performance servers and hardware are already deployable inside the data center, and WAN bandwidth can be provisioned beyond multi-Gbps. Unfortunately existing transport technology lacks the capability of fully utilizing the end-to-end capacity provided by underlying hardware platform, particularly over the wide area and traditional host system architectures limit per-packet processing to sub 10Gbps speeds. Intel and Aspera are collaborating to address and eliminate both bottlenecks.

Aspera’s fasp transport technology was created to overcome the bottlenecks of traditional transport protocols in moving large data over the wide area network. Aspera fasp has no theoretical throughput limit, and is practically constrained by the available network bandwidth and the hardware resources at both ends of the transfers.

Intel® DDIO and Non-Uniform Memory Access (NUMA) technologies were designed to deliver superior I/O throughput, and SR-IOV allows virtual machine platforms to bypass the hypervisor in order to directly access resources on the physical network interface for superior I/O performance particularly important for high-throughput large data transfer.

The goal of the project was to show the performance advantages expected for Aspera fasp transfers running on and Intel Xeon processor E5-2600 product family-based system in virtualized computing environments typical of cloud computing platforms.

Initial benchmark tests compared the performance of Aspera transfers on a high-performance Intel system versus a similar system that did not support Intel® DDIO. Additional tests focused on data transfer over a 10 Gigabit Intel® Ethernet connection between high-end Intel systems with built-in support for SR-IOV, and similar tests over WAN connection with varying degrees of latency (50ms – 500ms) and packet loss (0.1% - 5%).

Results confirmed the same transfer performance on WAN as LAN showing Aspera’s loss and delay tolerance, demonstrated a 300 percent throughput improvement versus a baseline system without SR-IOV and approximately the same throughput on virtual hosts enabled with Intel DDIO.

Details about the tests including full results are published in the Aspera and Intel whitepaper available at: